Timing rules & assumptions
- One instruction issues per cycle, in program order. Address calculation occurs at issue. Execution begins no earlier than the following cycle. The view starts before the first instruction. Next step reveals individual scheduling actions; Finish cycle advances to the next clock boundary. These teaching steps do not add cycles. Execution and CDB updates are shown before issue within each cycle.
- Latencies from your model: load 4, multiply 8, add 4, store 1, DADDUI 3, BNE 2 cycles. One non-pipelined unit per group. Multiply has 2 stations, add 3, loads 4, stores 4. One integer/branch slot is assumed.
- Qj and Qk are pending operand tags; Vj and Vk are captured values. A store has its own Qi data tag, independent of later register renaming. Zero indicates a ready operand.
- One result broadcasts per cycle, starting the cycle after execution finishes. Oldest finished instruction wins bus contention. Broadcast operands can execute next cycle. A station is reusable the cycle after writeback. Integer results also use the shared bus.
- Loads and stores execute in memory order, with one memory operation at a time. A store waits for its data, then updates memory at the end of its one execution cycle; it does not broadcast.
- Branches block further issue until resolved. There is no speculation or reorder buffer. Complete means result broadcast, memory write, or branch resolution—not merely the end of arithmetic execution.
- Blank initial F0 and F1 values are assumed to be 0; F2 = 1.20 and F3 = 6.00. R0 = 0, R1 = 2016, R2 = 1992. Other integer registers start at 0. Memory starts at 1992: 0, 2000: 1, 2008: 2, 2016: 3.