MIPS32 Simulator

Assemble • Execute • Pipeline • Optimize

Program (MIPS Assembly)

Ready

Simulation Controls

PC0x00400000
Instruction—
Instruction count0
Pipeline cycle0
StatusReady

Console

MIPS32 teaching simulator ready.

Instruction Pipeline (Classic 5-Stage MIPS)

Reorder instructions with ↑/↓ or drag rows. Step Cycle highlights the selected pipeline cycle. Step Instruction executes one architectural instruction and advances the PC.
IFIDEXMEMWBStall

Assembly Listing / Reorder

#AddressMachine CodeInstructionMove

Pipeline Options

WAR/WAW do not stall the classic in-order pipeline, but they matter when a student manually reorders code.

Performance Metrics

0Instructions
0Cycles
0Stalls
0.00CPI
0.00IPC

Detected Hazards / Dependencies

TypeProducerConsumerRegister / detailEffect

Registers (32 × 32-bit)

RegNameValue (hex)

Special Registers

HI0x00000000
LO0x00000000

Data Memory (Word View)

AddressValue (hex)
MIPS32 Teaching Simulator — Help

Assembler: supports labels, decimal/hex immediates, register names or numbers, comments (#, ;, //), and the core MIPS32 instructions used in a classic architecture course.

Pipeline: models IF → ID → EX → MEM → WB. With forwarding enabled, ordinary ALU RAW hazards are forwarded; an immediate load-use dependency inserts one stall. With forwarding off, RAW consumers wait for register write-back.

Reordering: drag rows or use ↑/↓. With “Protect semantic order” enabled, moves across RAW/WAR/WAW dependencies, branches/jumps, or potentially aliasing memory operations are blocked.

CPU execution: Step Instruction executes assembled instructions and updates registers/memory. Branch/jump delay slots are selectable. With Branch delay slot checked, the instruction immediately after a taken control transfer executes before the target is entered and JAL/JALR save PC + 8. With it unchecked, control transfers immediately and JAL/JALR save PC + 4. Step Cycle advances the highlighted pipeline-cycle indicator; it does not duplicate architectural execution.

Instruction subset: ADD/ADDU/SUB/SUBU, AND/OR/XOR/NOR, SLT/SLTU, shifts, JR/JALR, HI/LO multiply/divide moves and operations, ADDI/ADDIU, ANDI/ORI/XORI, SLTI/SLTIU, LUI, LW/SW/LB/LBU/LH/LHU/SB/SH, BEQ/BNE/BLEZ/BGTZ, J/JAL, plus SYSCALL, and NOP, MOVE, and LI pseudo-instructions. SYSCALL services 10 (exit) and 17 (exit with status in $a0) are supported.